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ltc3610 3610ff 0.47h 4.7f 10f 3 v in 4v to 24v v out 2.5v 12a 3610 ta01a 604k 0.1f i on v in sw boost run/ss i th v on sgnd intv cc fcb pgnd v fb v rng 0.22f 100f 2 31.83k ltc3610 470pf extv cc pgood 30.1k 9.5k 100pf load current (a) 0.01 efficiency (%) power loss (mw) 80 90 3610 ta 01b 70 50 60 85 95 75 55 65 0.1 1 10 100 1000 100 1 10 10000 v out = 2.5v power loss 12v power loss 5v v in = 12v v in = 5v features a pplications description 24v, 12a monolithic synchronous step-down dc/dc converter the ltc ? 3610 is a high effciency, monolithic synchronous step-down dc/dc converter that can deliver up to 12a output current from a 4v to 24v (28v maximum) input supply. it uses a valley current control architecture to de- liver very low duty cycle operation at high frequency with excellent transient response. the operating frequency is selected by an external resistor and is compensated for variations in v in and v out . the ltc3610 can be confgured for discontinuous or forced continuous operation at light load. forced continu- ous operation reduces noise and rf interference while discontinuous mode provides high effciency by reducing switching losses at light loads. fault protection is provided by internal foldback current limiting, an output overvoltage comparator and an optional short-circuit shutdown timer. soft-start capability for sup- ply sequencing is accomplished using an external timing capacitor. the regulator current limit is user programmable. a power good output voltage monitor indicates when the output is in regulation. the ltc3610 is available in a compact 9mm 9mm qfn package. 12a output current wide v in range = 4v to 24v internal n-channel mosfets true current mode control optimized for high step-down ratios t on(min) 100ns extremely fast transient response stable with ceramic c out 1% 0.6v voltage reference power good output voltage monitor adjustable on-time/switching frequency adjustable current limit programmable soft-start output overvoltage protection optional short-circuit shutdown timer low shutdown i q : 15a available in a 9mm 9mm 64-pin qfn package point of load regulation distributed power systems high effciency step-down converter effciency vs load current t ypical a pplication l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6100678, 6580258, 5847554, 6304066.
ltc3610 3610ff a bsolute maxi m u m r atings input supply voltage (v in , i on ) .................. 28v to C0.3v boosted topside driver supply voltage (boost) ................................................ 34v to C0.3v sw voltage ............................................ 28v to C0.3v intv cc , extv cc , (boost C sw), run/ss, pgood voltages ...................................... 7v to C0.3v fcb, v on , v rng voltages ............ intv cc + 0.3v to C0.3v i th , v fb voltages ....................................... 2.7v to C0.3v operating temperature range (note 4) ............................................. C40c to 125c junction temperature (note 2) ............................. 125c storage temperature range ................... C55c to 125c (note 1) symbol parameter conditions min typ max units main control loop v in operating input voltage range 4 24 v i q input dc supply current normal shutdown supply current 900 15 2000 30 a a v fb feedback reference voltage i th = 1.2v (note 3) 0.594 0.600 0.606 v v fb(linereg) feedback voltage line regulation v in = 4v to 28v, i th = 1.2v (note 3) 0.002 %/v p in c on f iguration top view wp package 64-lead (9mm 9mm) qfn multipad pgnd 1 pgnd 2 pgnd 3 sw 4 sw 5 sw 6 sw 7 sw 8 sw 9 sw 10 sw 11 pv in 12 pv in 13 pv in 14 pv in 15 pv in 16 48 sgnd 47 sgnd 46 sgnd 45 sgnd 44 extv cc 43 v fb 42 sgnd 41 i on 40 sgnd 39 fcb 38 i th 37 v rng 36 pgood 35 v on 34 sgnd 33 sgnd pv in 17 pv in 18 pv in 19 pv in 20 pv in 21 pv in 22 pv in 23 pv in 24 pv in 25 sw 26 nc 27 sgnd 28 boost 29 run/ss 30 sgnd 31 sgnd 32 64 pgnd 63 pgnd 62 pgnd 61 pgnd 60 pgnd 59 pgnd 58 pgnd 57 pgnd 56 pgnd 55 sw 54 intv cc 53 intv cc 52 sv in 51 sv in 50 sgnd 49 sgnd 68 sgnd 67 pv in 66 sw 65 pgnd t jmax = 125c, ja = 28c/w o r d er i n f or m ation lead free finish tape and reel part marking* package description temperature range ltc3610ewp#pbf ltc3610ewp#trpbf ltc3610wp 64-lead (9mm 9mm) plastic qfn C40c to 125c ltc3610iwp#pbf ltc3610iwp#trpbf ltc3610wp 64-lead (9mm 9mm) plastic qfn C40c to 125c lead based finish tape and reel part marking* package description temperature range ltc3610ewp ltc3610ewp#tr ltc3610wp 64-lead (9mm 9mm) plastic qfn C40c to 125c ltc3610iwp ltc3610iwp#tr ltc3610wp 64-lead (9mm 9mm) plastic qfn C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges.*the temperature grade is identifed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ e lectrical c haracteristics the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c (note 4). v in = 15v unless otherwise noted.
ltc3610 3610ff e lectrical c haracteristics the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c (note 4). v in = 15v unless otherwise noted. symbol parameter conditions min typ max units v fb(loadreg) feedback voltage load regulation i th = 0.5v to 1.9v (note 3) C0.05 C0.3 % i fb feedback input current v fb = 0.6v C5 50 na g m(ea) error amplifer transconductance i th = 1.2v (note 3) 1.4 1.7 2 ms v fcb forced continuous threshold 0.54 0.6 0.66 v i fcb forced continuous pin current v fcb = 0.6v C1 C2 a t on on-time i on = 60a, v on = 1.5v i on = 60a, v on = 0v 170 250 120 310 ns ns t on(min) minimum on-time i on = 180a, v on = 0v 60 100 ns t off(min) minimum off-time i on = 30a, v on = 1.5v 290 500 ns i valley(max) maximum valley current v rng = 0.5v, v fb = 0.56v, fcb = 0v v rng = 0v, v fb = 0.56v, fcb = 0v 7 10 16 19 a a i valley(min) maximum reverse valley current v rng = 0.5v, v fb = 0.64v, fcb = 0v v rng = 0v, v fb = 0.64v, fcb = 0v C6 C9 a a v fb(ov) output overvoltage fault threshold 7 10 13 % v run/ss(on) run pin start threshold 0.8 1.5 2 v v run/ss(le) run pin latchoff enable threshold run/ss pin rising 4 4.5 v v run/ss(lt) run pin latchoff threshold run/ss pin falling 3.5 4.2 v i run/ss(c) soft-start charge current v run/ss = 0v C0.5 C1.2 C3 a i run/ss(d) soft-start discharge current v run/ss = 4.5v, v fb = 0v 0.8 1.8 3 a v in(uvlo) undervoltage lockout v in falling 3.4 3.9 v v in(uvlor) undervoltage lockout release v in rising 3.5 4 v r ds(on) top switch on-resistance bottom switch on-resistance 12 6.5 16 10 m m internal v cc regulator v intvcc internal v cc voltage 6v < v in < 28v, v extvcc = 4v 4.7 5 5.5 v v ldo(loadreg) internal v cc load regulation i cc = 0ma to 20ma, v extvcc = 4v C0.1 2 % v extvcc extv cc switchover voltage i cc = 20ma, v extvcc rising 4.5 4.7 v v extvcc extv cc switch drop voltage i cc = 20ma, v extvcc = 5v 150 300 mv v extvcc(hys) extv cc switchover hysteresis 500 mv pgood output v fbh pgood upper threshold v fb rising 7 10 13 % v fbl pgood lower threshold v fb falling C7 C10 C13 % v fb(hys) pgood hysteresis v fb returning 1 2.5 % v pgl pgood low voltage i pgood = 5ma 0.15 0.4 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: t j is calculated from the ambient temperature t a and power dissipation p d as follows: t j = t a + (p d ? 28c/w) ( ja is simulated per jesd51-7 high effective thermal conductivity test board) jc = 0.24c/w ( jc is simulated when heat sink is applied at the bottom of the package). note 3: the ltc3610 is tested in a feedback loop that adjusts v fb to achieve a specifed error amplifer output voltage (i th ). note 4: the ltc3610 is tested under pulsed load conditions such that t j t a . the ltc3610e is guaranteed to meet performance specifcations from 0c to 125c. specifcations over the C40c to 125c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3610i is guaranteed over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature is determined by specifc operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors.
ltc3610 3610ff load current (a) 0.001 efficiency (%) 70 80 10 3610 g04 60 50 0.01 0.1 1 100 90 discontinuous mode continuous mode v in = 12v v out = 2.5v extv cc = 5v figure 6 circuit input voltage (v) 5 80 efficiency (%) 85 90 95 100 10 15 20 3610 g05 25 i load = 1a i load = 10a fcb = 5v figure 6 circuit input voltage (v) 5 frequency (khz) 480 520 25 3610 g06 440 400 10 15 20 640 600 560 i load = 10a fcb = 0v figure 6 circuit i load = 0a load current (a) 0 v out (%) 8 3610 g08 ?0.80 ?0.60 ?0.40 ?0.20 0.60 0.40 0.20 0 2 4 6 1210 0.80 figure 6 circuit load current (a) 0 i th voltage (v) 1.0 1.5 3610 g09 0.5 0 3 6 9 12 2.5 2.0 continuous mode discontinuous mode figure 6 circuit load current (a) 0 0 frequency (khz) 50 100 150 200 250 300 350 400 450 500 550 600 650 2 4 6 8 3610 g07 1210 continuous mode discontinuous mode t ypical p er f or m ance c haracteristics transient response transient response (discontinuous mode) start-up efciency vs load current efciency vs input voltage frequency vs input voltage frequency vs load current load regulation i th voltage vs load current load step 0a to 8a v in = 12v v out = 2.5v fcb = 0v figure 6 circuit 3610 g01 40s/div v out 100mv/div i l 5a/div i load 5a/div i load = 1a to 7a v in = 12v v out = 2.5v fcb = intv cc figure 6 circuit 3610 g02 40s/div v out 100mv/div i l 5a/div i load 5a/div v in = 12v v out = 2.5v r load = 0.5 figure 6 circuit 3610 g03 40ms/div run/ss 2v/div v out 1v/div i l 5a/div
ltc3610 3610ff input voltage (v) 4 maximum valley current (a) 18 16 14 12 10 3610 g17 4 6 8 7 10 13 16 19 282522 run/ss voltage (v) 1.65 0 maximum valley current limit (a) 3 6 9 12 18 15 1.90 2.15 2.65 2.90 3.15 3.40 2.40 3610 g15 i th voltage (v) 0 ?10 load current (a) ?5 0 5 20 15 10 25 0.5 1.0 1.5 2.0 3610 g10 2.5 3.0 v rng = 1v 0.7v 0.5v i on current (a) 1 10 on-time (ns) 100 1000 10000 10 100 3610 g11 v von = 0v v on voltage (v) 0 on-time (ns) 400 600 3610 g12 200 0 1 2 3 1000 i on = 30a 800 temperature (c) ?50 on-time (ns) 200 250 300 25 75 3610 g13 150 100 ?25 0 50 100 125 50 0 i ion = 30a v von = 0v v fb (v) 0 0 maximum valley current limit (a) 5 10 15 0.1 0.2 0.3 0.4 0.5 0.6 3610 g18 v rng voltage (v) 0.5 10 maximum valley current limit (a) 12 14 16 18 20 22 24 0.6 0.7 0.8 3610 g14 0.9 1.0 temperature (c) ?50 ?25 0 maximum valley current limit (a) 5 20 0 50 75 3610 g16 15 10 25 100 125 t ypical p er f or m ance c haracteristics l c i th v v rng ot i on c ot v on v ot t m v c l f m v c l v rng v m v c l runss v m v c l t i v m v c
ltc3610 3610ff temperature (c) ?50 ?25 0 extv cc switch resistance () 4 10 0 50 75 3610 g24 2 8 6 25 100 125 temperature (c) ?50 ?25 ?2 run/ss pin current (a) 0 3 0 50 75 3610 g25 ?1 2 1 25 100 125 pull-up current pull-down current temperature (c) ?50 ?25 1.0 g m (ms) 1.4 2.0 0 50 75 3610 g20 1.2 1.8 1.6 25 100 125 input voltage (v) 0 input current (a) shutdown current (a) 800 1000 1400 1200 15 25 3610 g21 600 400 5 10 20 30 200 0 30 25 15 5 40 35 20 10 0 extv cc open extv cc = 5v shutdown intv cc load current (ma) 0 intv cc (%) 0.10 0.20 0.30 40 3610 g22 0 ?0.20 ?0.10 ?0.40 ?0.30 10 20 30 50 t ypical p er f or m ance c haracteristics error amplifer g m vs temperature input and shutdown currents vs input voltage intv cc load regulation extv cc switch resistance vs temperature i extvcc vs frequency run/ss pin current vs temperature run/ss pin current vs temperature undervoltage lockout threshold vs temperature temperature (c) ?50 3.0 run/ss pin current (a) 3.5 4.0 4.5 5.0 ?25 0 25 50 3610 g26 75 100 125 latchoff enable latchoff threshold temperature (c) ?50 2.0 undervoltage lockout threshold (v) 2.5 3.0 3.5 4.0 ?25 0 25 50 3610 g27 75 100 125 temperature (c) ?50 0.58 feedback reference voltage (v) 0.59 0.60 0.61 0.62 ?25 0 25 50 3610 g19 75 100 125 feedback reference voltage vs temperature frequency (khz) 400 i extvcc (ma) 15 20 25 700 900 3610 g23 10 5 500 600 800 1000 0
ltc3610 3610ff p in functions pgnd (pins 1, 2, 3, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65): power ground. connect this pin closely to the (C) terminal of c vcc and the (C) terminal of c in . sw (pins 4, 5, 6, 7, 8, 9, 10, 11, 26, 55, 66): switch node connection to the inductor. the (C) terminal of the bootstrap capacitor c b also connects here. this pin swings from a diode voltage drop below ground up to v in . pv in (pins 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 67): main input supply. decouple this pin to power pgnd with the input capacitance c in . nc (pin 27): no connection. sgnd (pins 28, 31, 32, 33, 34, 40, 42, 45, 46, 47, 48, 49, 50, 68): signal ground. all small-signal components and compensation components should connect to this ground, which in turn connects to pgnd at one point. boost (pin 29): boosted floating driver supply. the (+) terminal of the bootstrap capacitor c b connects here. this pin swings from a diode voltage drop below intv cc up to v in + intv cc . run/ss (pin 30): run control and soft-start input. a capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/f) and the time delay for overcurrent latchoff (see applications information). forcing this pin below 0.8v shuts down the device. v on (pin 35): on-time voltage input. voltage trip point for the on-time comparator. tying this pin to the output volt- age or an external resistive divider from the output makes the on-time proportional to v out . the comparator input defaults to 0.7v when the pin is grounded and defaults to 2.4v when the pin is tied to intv cc . tie this pin to intv cc in high v out applications to use a lower r on value. pgood (pin 36): power good output. open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point. v rng (pin 37): current limit range input. the voltage at this pin adjusts maximum valley current and can be set from 0.5v to 0.7v by a resistive divider from intv cc . it defaults to 0.7v if the v rng pin is tied to ground which results in a typical 19a current limit. i th (pin 38): current control threshold and error amplifer compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.8v corresponding to zero sense voltage (zero current). fcb (pin 39): forced continuous input. tie this pin to ground to force continuous synchronous operation at low load, to intv cc to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. i on (pin 41): on-time current input. tie a resistor from v in to this pin to set the one-shot timer current and thereby set the switching frequency. v fb (pin 43): error amplifer feedback input. this pin connects the error amplifer input to an external resistive divider from v out . extv cc (pin 44): external v cc input. when extv cc exceeds 4.7v, an internal switch connects this pin to intv cc and shuts down the internal regulator so that controller and gate drive power is drawn from extv cc . do not exceed 7v at this pin and ensure that extv cc < v in . sv in (pins 51, 52): supply pin for internal pwm controller. intv cc (pins 53, 54): internal 5v regulator output. the driver and control circuits are powered from this voltage. decouple this pin to power ground with a minimum of 4.7f low esr tantalum or ceramic capacitor.
ltc3610 3610ff functional diagra m 0.7v 1.4v v rng ? + ? + ? + ? + ? + i on v on i cmp 0.7v fcb extv cc sv in 1a r on v von i ion t on = (10pf) r s q 20k i rev ( 0.5 to 2) 1v shdn switch logic on fcnt 0.6v ? + 4.7v ov 1 240k 0.4v i th c ss ea ss 0.6v + ? + ? 3.3 run/ss 3610 fd sgnd r1 run shdn pgnd pgood v fb sw pv in c in boost m1 m2 intv cc ? + ? + uv 0.54v ov 0.66v 6v 0.6v ref 5v reg r2 2.4v 37 35 41 39 44 29 nc 27 4, 5, 6, 7, 8, 9, 10, 11, 26, 55, 66 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 67 53, 54 51, 52 1, 2, 3, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65 28, 31, 32, 33, 34, 40, 42, 45, 46, 47, 48, 49, 50, 68 36 43 30 38 v out l1 c out c vcc + q1q3 q4q2 0.8v i thb q6 c b d b f 1.2a
ltc3610 3610ff o peration main control loop the ltc3610 is a high effciency monolithic synchronous, step-down dc/dc converter utilizing a constant on-time, current mode architecture. it operates from an input voltage range of 4v to 24v and provides a regulated output voltage at up to 12a of output current. the internal synchronous power switch increases effciency and eliminates the need for an external schottky diode. in normal operation, the top mosfet is turned on for a fxed interval determined by a one-shot timer ost. when the top mosfet is turned off, the bottom mosfet is turned on until the current comparator i cmp trips, restarting the one-shot timer and initiating the next cycle. inductor current is determined by sensing the voltage between the pgnd and sw pins using the bottom mosfet on-resistance. the voltage on the i th pin sets the comparator threshold corresponding to inductor valley current. the error amplifer, ea, adjusts this voltage by comparing the feedback signal v fb from the output voltage with an internal 0.6v reference. if the load current increases, it causes a drop in the feedback voltage relative to the reference. the i th voltage then rises until the average inductor current again matches the load current. at light load, the inductor current can drop to zero and become negative. this is detected by current reversal comparator i rev which then shuts off m2 (see func- tional diagram), resulting in discontinuous operation. both switches will remain off with the output capacitor supplying the load current until the i th voltage rises above the zero current level (0.8v) to initiate another cycle. discontinu- ous mode operation is disabled by comparator f when the fcb pin is brought below 0.6v, forcing continuous synchronous operation. the operating frequency is determined implicitly by the top mosfet on-time and the duty cycle required to main- tain regulation. the one-shot timer generates an on-time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in v in . the nominal frequency can be adjusted with an external resistor, r on . overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback volt- age exits a 10% window around the regulation point. furthermore, in an overvoltage condition, m1 is turned off and m2 is turned on and held on until the overvoltage condition clears. foldback current limiting is provided if the output is shorted to ground. as v fb drops, the buffered current threshold voltage i thb is pulled down by clamp q3 to a 1v level set by q4 and q6. this reduces the inductor valley current level to one sixth of its maximum value as v fb approaches 0v. pulling the run/ss pin low forces the controller into its shutdown state, turning off both m1 and m2. releasing the pin allows an internal 1.2a current source to charge up an external soft-start capacitor, c ss . when this voltage reaches 1.5v, the controller turns on and begins switching, but with the i th voltage clamped at approximately 0.6v below the run/ss voltage. as c ss continues to charge, the soft-start current limit is removed. intv cc /extv cc power power for the top and bottom mosfet drivers and most of the internal controller circuitry is derived from the intv cc pin. the top mosfet driver is powered from a foating bootstrap capacitor c b . this capacitor is recharged from intv cc through an external schottky diode, d b , when the top mosfet is turned off. when the extv cc pin is grounded, an internal 5v low dropout regulator supplies the intv cc power from v in . if extv cc rises above 4.7v, the internal regulator is turned off, and an internal switch connects extv cc to intv cc . this allows a high effciency source connected to extv cc , such as an external 5v sup- ply or a secondary output from the converter, to provide the intv cc power. voltages up to 7v can be applied to extv cc for additional gate drive. if the input voltage is low and intv cc drops below 3.5v, undervoltage lockout circuitry prevents the power switches from turning on.
ltc3610 0 3610ff a pplications i n f or m ation the basic ltc3610 application circuit is shown on the front page of this data sheet. external component selection is primarily determined by the maximum load current. the ltc3610 uses the on-resistance of the synchronous power mosfet for determining the inductor current. the desired amount of ripple current and operating frequency also determines the inductor value. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient specifcation. v on and pgood the ltc3610 has an open-drain pgood output that indicates when the output voltage is within 10 % of the regulation point. the ltc3610 also has a v on pin that allows the on-time to be adjusted. tying the v on pin high results in lower values for r on which is useful in high v out applications. the v on pin also provides a means to adjust the on-time to maintain constant frequency operation in applications where v out changes and to correct minor frequency shifts with changes in load current. v rng pin and i limit adjust the v rng pin is used to adjust the maximum inductor valley current, which in turn determines the maximum average output current that the ltc3610 can deliver. the maximum output current is given by: i out(max) = i valley(max) + 1/2 i l the i valley(max) is shown in the fgure maximum valley current limit vs v rng voltage in the typical performance characteristics. an external resistor divider from intv cc can be used to set the voltage on the v rng pin from 0.5v to 1v, or it can be simply tied to ground force a default value equivalent to 0.7v. when setting current limit, ensure that the junc- tion temperature does not exceed the maximum rating of 125c. do not foat the v rng pin. operating frequency the choice of operating frequency is a trade-off between effciency and component size. low frequency operation improves effciency by reducing mosfet switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. the operating frequency of ltc3610 applications is de- termined implicitly by the one-shot timer that controls the on-time t on of the top mosfet switch. the on-time is set by the current into the i on pin and the voltage at the v on pin according to: t v i pf on von ion = ( )10 tying a resistor, r on , from v in to the i on pin yields an on-time inversely proportional to v in . the current out of the i on pin is: i v r ion in on = for a step-down converter, this results in approximately constant frequency operation as the input supply varies: f v v r pf h out von on z = ( ) [ ] 10 to hold frequency constant during output voltage changes, tie the v on pin to v out or to a resistive divider from v out when v out > 2.4v. the v on pin has internal clamps that limit its input to the one-shot timer. if the pin is tied below 0.7v, the input to the one-shot is clamped at 0.7v. similarly, if the pin is tied above 2.4v, the input is clamped at 2.4v. in high v out applications, tying v on to intv cc so that the comparator input is 2.4v results in a lower value for r on . figures 1a and 1b show how r on relates to switching frequency for several common output voltages.
ltc3610 3610ff a pplications i n f or m ation figure 1a. switching frequency vs r on (v on = 0v) figure 1b. switching frequency vs r on (v on = intv cc ) because the voltage at the i on pin is about 0.7v, the cur- rent into this pin is not exactly inversely proportional to v in , especially in applications with lower input voltages. to correct for this error, an additional resistor r on2 con- nected from the i on pin to the 5v intv cc supply will further stabilize the frequency. r v v r on on 2 5 0 7 = . changes in the load current magnitude will also cause frequency shift. parasitic resistance in the mosfet switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. by lengthening the on-time slightly as current increases, constant frequency operation can be maintained. this is accomplished with a resistive divider from the i th pin to the v on pin and v out . the values required will depend on the parasitic resistances in the specifc application. a good starting point is to feed about 25% of the voltage change at the i th pin to the v on pin as shown in figure 2a. place capacitance on the v on pin to flter out the i th variations at the switching frequency. the resistor load on i th reduces the dc gain of the error amp and degrades load regulation, which can be avoided by using the pnp emitter follower of figure 2b. minimum off-time and dropout operation the minimum off-time, t off(min), is the smallest amount of time that the ltc3610 is capable of turning on the bot- tom mosfet, tripping the current comparator and turning the mosfet back off. this time is generally about 250ns. the minimum off-time limit imposes a maximum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: v v t t t in min out on off min on ( ) ( ) = + a plot of maximum duty cycle vs frequency is shown in figure 3. setting the output voltage the ltc3611 develops a 0.6v reference voltage between the feedback pin, v fb , and the signal ground as shown in figure 6. the output voltage is set by a resistive divider according to the following formula: v out = 0.6v 1 + r2 r1 ? ? ? ? ? ? to improve the frequency response, a feedforward capaci- tor c1 may also be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw trace. r on (k) 100 100 switching frequency (khz) 1000 1000 10000 3610 f01a v out = 3.3v v out = 1.5v v out = 2.5v r on (k) 100 100 switching frequency (khz) 1000 1000 10000 3610 f01b v out = 3.3v v out = 12v v out = 5v
ltc3610 3610ff a pplications i n f or m ation inductor selection given the desired input and output voltages, the induc- tor value and operating frequency determine the ripple current: i l = v out f l ? ? ? ? ? ? 1? v out v in ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest effciency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a trade-off between component size, effciency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a specifed maximum, the inductance should be chosen according to: l = v out f i l(max) ? ? ? ? ? ? 1? v out v in(max) ? ? ? ? ? ? once the value for l is known, the type of inductor must be selected. high effciency converters generally cannot afford the core loss found in low cost powdered iron cores. a variety of inductors designed for high current, low volt- age applications are available from manufacturers such as sumida, panasonic, coiltronics, coilcraft and toko. c in and c out selection the input capacitance c in is required to flter the square wave current at the drain of the top mosfet. use a low esr capacitor sized to handle the maximum rms current. i rms ? i out(max) v out v in v in v out ? 1 this formula has a maximum at v in = 2v out , where i rms = i out(max) /2. this simple worst-case condition is commonly used for design because even signifcant de- viations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple v out is approximately bounded by: v out i l esr + 1 8fc out ? ? ? ? ? ? figure 3. maximum switching frequency vs duty cycle 2.0 1.5 1.0 0.5 0 0 0.25 0.50 0.75 3610 f03 1.0 dropout region duty cycle (v out /v in ) switching frequency (mhz) figure 2. correcting frequency shift with load current changes c von 0.01f r von2 100k r von1 30k c c v out r c (2a) (2b) v on i th ltc3610 c von 0.01f r von2 10k q1 2n5087 r von1 3k 10k c c 3610 f02 v out intv cc r c v on i th ltc3610
ltc3610 3610ff since i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfed, the capacitance is adequate for fltering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount pack- ages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have signifcantly higher esr, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteris- tics but can have a high voltage coeffcient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signifcant ringing. when used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. to dampen input voltage transients, add a small 5f to 50f aluminum electrolytic capacitor with an esr in the range of 0.5 to 2. high performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. t op mosfet driver supply (c b , d b ) an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from intv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store about 100 times the gate charge required by the top mosfet. in most applications an 0.1f to 0.47f, x5r or x7r dielectric capacitor is adequate. discontinuous mode operation and fcb pin the fcb pin determines whether the bottom mosfet remains on when current reverses in the inductor. tying this pin above its 0.6v threshold enables discontinuous operation where the bottom mosfet turns off when in- ductor current reverses. the load current at which current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and will vary with changes in v in . tying the fcb pin below the 0.6v threshold forces continuous synchronous operation, al- lowing current to reverse at light loads and maintaining high frequency operation. in addition to providing a logic input to force continuous operation, the fcb pin provides a means to maintain a fyback winding output when the primary is operating in discontinuous mode. the secondary output v out2 is normally set as shown in figure 4 by the turns ratio n of the transformer. however, if the controller goes into discontinuous mode and halts switching due to a light primary load current, then v out2 will droop. an external resistor divider from v out2 to the fcb pin sets a minimum voltage v out2(min) below which continuous operation is forced until v out2 has risen above its minimum: v out2(min) = 0.6v 1 + r4 r3 ? ? ? ? ? ? fault conditions: current limit and foldback the ltc3610 has a current mode controller which inher- ently limits the cycle-by-cycle inductor current not only in steady state operation but also in transient. to further limit current in the event of a short circuit to ground, the ltc3610 includes foldback current limiting. if the output falls by more than 25%, then the maximum sense voltage is progressively lowered to about one sixth of its full value. a pplications i n f or m ation
ltc3610 3610ff a pplications i n f or m ation intv cc regulator and extv cc connection an internal p-channel low dropout regulator produces the 5v supply that powers the drivers and internal circuitry within the ltc3610. the intv cc pin can supply up to 50ma rms and must be bypassed to ground with a minimum of 4.7f tantalum or ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers. the extv cc pin can be used to provide mosfet gate drive and control power from the output or another external source during normal operation. whenever the extv cc pin is above 4.7v the internal 5v regulator is shut off and an internal 50ma p-channel switch connects the extv cc pin to intv cc . intv cc power is supplied from extv cc until this pin drops below 4.5v. do not apply more than 7v to the extv cc pin and ensure that extv cc v in . the following list summarizes the possible connections for extv cc : 1. extv cc grounded. intv cc is always powered from the internal 5v regulator. 2. e xtv cc connected to an external supply. a high effciency supply compatible with the mosfet gate drive require- ments (typically 5v) can improve overall effciency. 3. ext v cc connected to an output derived boost network. the low voltage output can be boosted using a charge pump or fyback winding to greater than 4.7v. the system will start-up using the internal linear regulator until the boosted output supply is available. soft-start and latchoff with the run/ss pin the run/ss pin provides a means to shut down the ltc3610 as well as a timer for soft-start and overcurrent latchoff. pulling the run/ss pin below 0.8v puts the ltc3610 into a low quiescent current shutdown (i q < 30a). releasing the pin allows an internal 1.2a current source to charge up the external timing capacitor c ss . if run/ss has been pulled all the way to ground, there is a delay before start- ing of about: t delay = 1.5v 1.2 a c ss = 1.3s/ f ( ) c ss figure 4. secondary output loop and extv cc connection ltc3610 sgnd 48 sgnd 47 sgnd 46 sgnd 45 extv cc 44 v fb 43 sgnd 42 i on 41 r4 sgnd 40 fcb 39 i th 38 v rng 37 pgood 36 v on 35 sgnd 34 sgnd sgnd gnd 33 pv in 17 pv in 18 pv in 19 pv in 20 pv in 21 pv in 22 pv in 23 pv in 24 pv in 25 sw sw sw 26 nc 27 sgnd 28 boost 29 run/ss 30 sgnd 31 sgnd 32 pgnd 64 pgnd 63 pgnd 62 pgnd 61 pgnd 60 pgnd 59 pgnd 58 pgnd 57 pgnd 56 sw 55 intv cc 54 intv cc 53 sv in 52 sv in 51 sgnd 50 sgnd 49 pgnd 1 pgnd 2 pgnd 3 sw 4 sw 5 sw 6 sw 7 sw 8 sw 9 sw 10 sw 11 pv in v in 12 pv in 13 pv in 14 pv in 15 pv in 16 3610 f04 c sec 1f v out2 v out1 c out c in in4148 optional extv cc connection 5v < v out2 < 7v t1 1:n r3 + + ? ? +
ltc3610 3610ff 3.3v or 5v run/ss v in intv cc run/ss d1 (5a) (5b) d2* c ss r ss * c ss *optional to override overcurrent latchoff r ss * 3610 f05 2n7002 a pplications i n f or m ation figure 5. run/ss pin interfacing with latchoff defeated when the voltage on run/ss reaches 1.5v, the ltc3610 begins operating with a clamp on i th of approximately 0.9v. as the run/ss voltage rises to 3v, the clamp on i th is raised until its full 2.4v range is available. this takes an additional 1.3s/f, during which the load current is folded back until the output reaches 75% of its fnal value. after the controller has been started and given adequate time to charge up the output capacitor, c ss is used as a short-circuit timer. after the run/ss pin charges above 4v, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. a 1.8a current then begins discharging c ss . if the fault condition persists until the run/ss pin drops to 3.5v, then the controller turns off both power mosfets, shutting down the converter permanently. the run/ss pin must be actively pulled down to ground in order to restart operation. t h e overcurrent protection timer requires that the soft - start timing capacitor, c ss , be made large enough to guarantee that the output is in regulation by the time c ss has reached the 4v threshold. in general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. a minimum soft-start capacitor can be estimated from: c ss > c out v out r sense (10 C4 [f/v s]) generally 0.1f is more than suffcient. overcurrent latchoff operation is not always needed or de- sired. load current is already limited during a short-circuit by the current foldback circuitry and latchoff operation can prove annoying during troubleshooting. the feature can be overridden by adding a pull-up current greater than 5a to the run/ss pin. the additional current prevents the discharge of c ss during a fault and also shortens the soft-start period. using a resistor to v in as shown in fig- ure 5a is simple, but slightly increases shutdown current. connecting a resistor to intv cc as shown in figure 5b eliminates the additional shutdown current, but requires a diode to isolate c ss . any pull-up network must be able to pull run/ss above the 4.2v maximum threshold of the latchoff circuit and overcome the 4a maximum discharge current. effciency considerations the percent effciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in ltc3610 circuits: 1. dc i 2 r losses. these arise from the resistance of the internal resistance of the mosfets, inductor and pc board traces and cause the effciency to drop at high output currents. in continuous mode the average output current fows through l, but is chopped between the top and bottom mosfets. the dc i 2 r loss for one mosfet can simply be determined by [r ds(on) + r l ] ? i o . 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated re- gion during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other factors. the loss is signifcant at input voltages above 20v and can be estimated from: t ransition loss ? (1.7a C1 ) v in 2 i out c rss f 3. intv cc current. this is the sum of the mosfet driver and control currents. this loss can be reduced by sup- plying intv cc current through the extv cc pin from a high effciency source, such as an output derived boost network or alternate supply if available.
ltc3610 3610ff a pplications i n f or m ation 4. c in loss. the input capacitor has the diffcult job of fltering the large rms input current to the regulator. it must have a very low esr to minimize the ac i 2 r loss and suffcient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. other losses, including c out esr loss, schottky diode d1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. when making adjustments to improve effciency, the input current is the best indicator of changes in effciency. if you make a change and the input current decreases, then the effciency has increased. if there is no change in input current, then there is no change in effciency. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or dis- charge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the i th pin external components shown in figure 6 will provide adequate compensation for most applications. for a detailed explanation of switching control loop theory see application note 76. design example as a design example, take a supply with the following specifcations: v in = 5v to 24v (12v nominal), v out = 2.5v 5%, i out(max) = 12a, f = 550khz. first, calculate the timing resistor with v on = v out : r khz pf k on = ( )( ) = 1 550 10 182 and choose the inductor for about 40% ripple current at the maximum v in : l = 2.5v 550khz ( ) 0.4 ( ) 12a ( ) 1? 2.5v 28v ? ? ? ? ? ? = 0.86h selecting a standard value of 0.82h results in a maximum ripple current of: i l = 2.5v 550khz ( ) 0.82 h ( ) 1? 2.5v 12v ? ? ? ? ? ? = 4.4a next, set up v rng voltage and check the i limit . tying v rng to 0.5v will set the typical current limit to 16a, and tying v rng to gnd will result in a typical current around 19a. c in is chosen for an rms current rating of about 5a at 85c. the output capacitors are chosen for a low esr of 0.013 to minimize output voltage changes due to inductor ripple current and load steps. the ripple voltage will be only: v out(ripple) = i l(max) (esr) = (4.4a) (0.013) = 57mv however , a 0a to 10a load step will cause an output change of up to: v out(step) = i load (esr) = (10a) (0.013) = 130mv an optional 22f ceramic output capacitor is included to minimize the effect of esl in the output ripple. the complete circuit is shown in figure 6. how to reduce sw ringing as with any switching regulator, there will be voltage ring- ing on the sw node, especially for high input voltages. the ringing amplitude and duration is dependent on the switching speed (gate drive), layout (parasitic inductance) and mosfet output capacitance. this ringing contributes to the overall emi, noise and high frequency ripple. one way to reduce ringing is to optimize layout. a good layout minimizes parasitic inductance. adding rc snubbers from sw to gnd is also an effective way to reduce ringing. finally, adding a resistor in series with the boost pin will slow down the mosfet turn-on slew rate to dampen ringing, but at the cost of reduced effciency. note that since the ic is buffered from the high frequency transients by pcb and bondwire inductances, the ringing by itself is normally not a concern for controller reliability.
ltc3610 3610ff figure 6. design example: 5v to 24v input to 2.5v/12a at 550khz v out 2.5v at 12a gnd gnd v in v in 5v to 24v c out1 220f 2 c5 22f 6.3v l1 0.8h c in 10f 35v 3 + c6 10f 35v + (optional) (optional) c in : taiyo yuden gmk325bj106mm-b c out : sanyo 10tpe220ml l1: cdep85np-r80mc-50 c5: murata grm31cr60j226ke19 ltc3610 sgnd 48 sgnd 47 sgnd 46 sgnd 45 extv cc extv cc 44 v fb 43 sgnd 42 i on 41 sgnd 40 fcb 39 i th 38 v rng 37 pgood 36 v on 35 sgnd 34 sgnd gnd v out v out 33 pv in 17 pv in 18 pv in 19 pv in 20 pv in 21 pv in 22 pv in 23 pv in 24 pv in 25 sw sw sw sw 26 nc 27 sgnd 28 boost 29 run/ss 30 sgnd 31 sgnd 32 pgnd 64 pgnd 63 pgnd 62 pgnd 61 pgnd 60 pgnd 59 pgnd 58 pgnd 57 pgnd 56 sw 55 intv cc intv cc intv cc 54 intv cc intv cc 53 sv in v in 52 sv in 51 sgnd 50 sgnd 49 pgnd 1 pgnd 2 pgnd 3 sw 4 sw 5 sw 6 sw 7 sw 8 sw 9 sw 10 sw 11 pv in v in 12 pv in 13 pv in 14 pv in 15 pv in 16 3610 f06 c f 0.1f 25v r f1 1 c vcc 4.7f 6.3v c3 c on 0.01f c4 0.01f c2 c1 c b1 0.22f d b cmdsh-3 c ss 0.1f v in r ss1 510k (optional) (optional) (optional) (optional) r1 9.5k 1% r2 30.1k 1% r von 0 r pg1 100k r on 182k 1% r5 31.84k r3 0 c c1 470pf c c2 100pf (optional) a pplications i n f or m ation pc board layout checklist when laying out a pc board follow one of the two sug- gested approaches. the simple pc board layout requires a dedicated ground plane layer. also, for higher currents, a multilayer board is recommended to help with heat sinking of power components. ? the ground plane layer should not have any traces and it should be as close as possible to the layer with the ltc3610. ? place c in and c out all in one compact area, close to the ltc3610. it may help to have some components on the bottom side of the board. ? keep small-signal components close to the l tc3610. ? ground connections (including ltc3610 sgnd and pgnd) should be made through immediate vias to the ground plane. use several larger vias for power components. ? use a compact plane for the switch node (sw) to improve cooling of the mosfets and to keep emi down. ? use planes for v in and v out to maintain good voltage fltering and to keep power losses low. ? flood all unused areas on all layers with copper. flood- ing with copper reduces the temperature rise of power components. connect these copper areas to any dc net (v in , v out , gnd or to any other dc rail in your system).
ltc3610 3610ff figure 7. ltc3610 layout diagram ltc3610 sgnd 48 sgnd 47 sgnd 46 sgnd 45 extv cc 44 v fb 43 sgnd 42 i on 41 sgnd 40 fcb 39 i th 38 v rng 37 pgood 36 v on 35 sgnd 34 33 pv in 17 pv in 18 pv in 19 pv in 20 pv in 21 pv in 22 pv in 23 pv in 24 pv in 25 sw 26 nc 27 sgnd 28 boost 29 run/ss 30 sgnd 31 sgnd 32 pgnd 64 pgnd 63 pgnd 62 pgnd 61 pgnd 60 pgnd 59 pgnd 58 pgnd 57 pgnd 56 sw sw 55 intv cc 54 intv cc 53 sv in 52 sv in 51 sgnd 50 sgnd 49 pgnd 1 pgnd 2 pgnd 3 sw 4 sw 5 sw 6 sw 7 sw 8 sw 9 sw 10 sw 11 pv in 12 pv in 13 pv in 14 pv in 15 pv in 16 3610 f07 c in c out v out c vcc c b d b c ss r1 r f r on r2 r c c c1 c c2 a pplications i n f or m ation when laying out a printed circuit board without a ground plane, use the following checklist to ensure proper opera- tion of the controller. these items are also illustrated in figure 7. ? segregate the signal and power grounds. all small- signal components should return to the sgnd pin at one point, which is then tied to the pgnd pin. ? connect the input capacitor(s), c in , close to the ic. this capacitor carries the mosfet ac current. ? keep the high dv/dt sw, boost and tg nodes away from sensitive small-signal nodes. ? connect the intv cc decoupling capacitor , c vcc , closely to the intv cc and pgnd pins. ? connect the top driver boost capacitor , c b , closely to the boost and sw pins. ? connect the v in pin decoupling capacitor , c f , closely to the v in and pgnd pins.
ltc3610 3610ff t ypical a pplications ltc3610 sgnd 48 sgnd 47 sgnd 46 sgnd 45 extv cc extv cc 44 v fb 43 sgnd 42 i on 41 sgnd 40 fcb 39 i th 38 v rng 37 pgood 36 v on 35 sgnd 34 sgnd gnd v out 1.5v at 12a v out v out gnd gnd 33 pv in 17 pv in 18 pv in 19 pv in 20 pv in 21 pv in 22 pv in 23 pv in 24 pv in 25 sw sw 26 nc 27 sgnd 28 boost 29 run/ss 30 sgnd 31 sgnd 32 pgnd 64 pgnd 63 pgnd 62 pgnd 61 pgnd 60 pgnd 59 pgnd 58 pgnd 57 pgnd 56 sw 55 intv cc intv cc intv cc 54 intv cc intv cc 53 sv in v in2 = 5v 52 sv in 51 sgnd 50 sgnd 49 pgnd 1 pgnd 2 pgnd 3 sw 4 sw 5 sw 6 sw 7 sw 8 sw 9 sw 10 sw 11 pv in v in v in 12 pv in 13 pv in 14 pv in 15 pv in 16 3610 ta02 c out1 220f 2 c5 22f 6.3v l1 0.36h c f 0.1f 25v c in 10f 3 c vcc 4.7f 6.3v + c6 10f 35v + (optional) (optional) c in : taiyo yuden tmk432bj106mm c out1 : sanyo 10tpe220ml l1: toko fdh1040-36m c5: taiyo yuden jmk316bj226ml-t c von c on 0.01f c4 0.01f c2 c1 c b1 0.22f c ss 0.1f v in r ss1 510k (optional) (optional) (optional) (optional) (optional) (optional) r1 20.43k 1% r2 30.1k 1% r von r pg1 100k r on 113k 1% r5 11.15k c c1 470pf c c2 100pf v in 3.3v 3.3v input to 1.5v/12a at 750khz
ltc3610 0 3610ff 5v to 24v input to 1.2v/12a at 550khz t ypical a pplications v out 1.2v at 12a gnd gnd v in c out1 220f 2 c5 22f 6.3v l1 0.52h c in 10f 25v 3 + c6 10f 35v + (optional) (optional) c5: taiyo yuden jmk316bj226ml-t c in : taiyo yuden tmk432bj106mm c out1 : sanyo 10tpe220ml l1: wurth 744310055 ltc3610 sgnd 48 sgnd 47 sgnd 46 sgnd 45 extv cc extv cc 44 v fb 43 sgnd 42 i on 41 sgnd 40 fcb 39 i th 38 v rng 37 pgood 36 v on 35 sgnd 34 sgnd sgnd gnd v out v out 33 pv in 17 pv in 18 pv in 19 pv in 20 pv in 21 pv in 22 pv in 23 pv in 24 pv in 25 sw 26 nc 27 sgnd 28 29 run/ss 30 sgnd 31 sgnd 32 pgnd 64 pgnd 63 pgnd 62 pgnd 61 pgnd 60 pgnd 59 pgnd 58 pgnd 57 pgnd 56 sw 55 intv cc intv cc 54 intv cc intv cc 53 sv in v in 52 sv in 51 sgnd 50 sgnd 49 pgnd 1 pgnd 2 pgnd 3 sw 4 sw 5 sw 6 sw 7 sw 8 sw 9 sw 10 sw 11 pv in v in 12 pv in 13 pv in 14 pv in 15 pv in 16 3610 ta03 c f 0.1f 25v r f1 1 c vcc 4.7f 6.3v c on 0.01f c4 0.01f c2 c1 d b cmdsh-3 c ss 0.1f v in r ss1 510k (optional) (optional) (optional) (optional) r1 30k 1% r2 30.1k 1% r pg1 100k r on 301k 1% r5 31.84k c c1 470pf c c2 100pf c von (optional) r von v in 5v to 24v sw boost intv cc c b1 0.22f
ltc3610 3610ff t ypical a pplications 5v to 24v input to 1.8v/12a all ceramic 1mhz v out 1.8v at 12a gnd v in v in 5v to 24v c out 100f 2 c5 22f 6.3v l1 0.47h c in 10f 25v 3 (optional) c out : taiyo yuden jmk325bj107my l1: tokin mplc0730 c5: taiyo yuden jmk316bj226ml-t ltc3610 sgnd 48 sgnd 47 sgnd 46 sgnd 45 extv cc extv cc 44 v fb 43 sgnd 42 i on 41 sgnd 40 fcb 39 i th 38 v rng 37 pgood 36 v on 35 sgnd 34 sgnd gnd v out v out 33 pv in 17 pv in 18 pv in 19 pv in 20 pv in 21 pv in 22 pv in 23 pv in 24 pv in 25 sw 26 nc 27 sgnd 28 29 run/ss 30 sgnd 31 sgnd 32 pgnd 64 pgnd 63 pgnd 62 pgnd 61 pgnd 60 pgnd 59 pgnd 58 pgnd 57 pgnd 56 sw 55 intv cc intv cc 54 intv cc intv cc 53 sv in v in 52 sv in 51 sgnd 50 sgnd 49 pgnd 1 pgnd 2 pgnd 3 sw 4 sw 5 sw 6 sw 7 sw 8 sw 9 sw 10 sw 11 pv in v in 12 pv in 13 pv in 14 pv in 15 pv in 16 3610 ta04 c f 0.1f 25v r f1 1 c vcc 4.7f 6.3v c on 0.01f c4 0.01f c2 c1 d b cmdsh-3 c ss 0.1f v in r ss1 510k (optional) (optional) (optional) (optional) r1 10k 1% r2 20k 1% r pg1 100k r on 102k 1% r5 18.7k c c1 560pf c c2 100pf c von (optional) (optional) r von sw boost intv cc c b1 0.22f
ltc3610 3610ff p ackage description wp package 64-lead qfn multipad (9mm 9mm) (reference ltc dwg # 05-08-1812 rev a) 9.00 bsc 9.00 bsc 17 16 32 33 bottom view (bottom metallization details) top view 0.90 0.10 // ccc c 0.20 ref 0.00 ? 0.05 0.30 ? 0.50 wp64 qfn rev a 0707 0.20 ? 0.30 nx b seating plane 6 5 0.08 c aaa c aaa c m ac b bbb nx a b 2x 2x 3.30 1.19 49 48 50 51 52 53 54 64 1 1.39 1.17 0.53 (2x) 1.92 2.01 3.06 4.10 3.30 0.30 (2x) 0.95 3.50 0.87 3.60 0.50 1.81 2.04 2.98 3.99 4.53 note: 1. dimensioning and tolerancing conform to asme y14.5m-1994 2. all dimensions are in millimeters, angles are in degrees () 3. n is the total number of terminals 4. the location of the terminal #1 identifier and terminal numbering convention conforms to jedec publication 95 spp-002 6 coplanarity applies to the terminals and all other surface metallization 5 dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. symbol aaa bbb ccc tolerance 0.15 0.10 0.10 wp package 64-lead qfn multipad (9mm 9mm) (reference ltc dwg # 05-08-1812 rev a) 3.85 1.42 pad 1 corner recommended solder pad layout top view 0.30 ? 0.50 3.30 1.19 1.17 1.92 2.01 3.06 4.10 0.53 (2x) 1.39 3.30 0.30 (2x) 2.30 3.50 0.87 3.60 pin 1 0.50 1.81 2.04 2.98 3.99 4.53 0.20 ? 0.30 3.85 1.42 0.95 1.30 1.30
ltc3610 3610ff information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h istory rev date description page number f 07/10 i-grade part added. refected throughout the data sheet. 1 to 24 (revision history begins at rev f)
ltc3610 3610ff linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0710 rev f ? printed in usa v out 12v at 5a gnd gnd v in v in 14v to 24v c out 180f 16v c5 22f 25v l1 5.7h c in 10f 25v 3 + c6 10f 35v + (optional) (optional) c in : taiyo yuden tmk432bj106mm c out : sanyo 16svp180mx l1: sumida cdep1055r7 ltc3610 sgnd 48 sgnd 47 sgnd 46 sgnd 45 extv cc extv cc 44 v fb 43 sgnd 42 i on 41 sgnd 40 fcb 39 i th 38 v rng 37 pgood 36 v on 35 sgnd 34 sgnd gnd intv cc v out 33 pv in 17 pv in 18 pv in 19 pv in 20 pv in 21 pv in 22 pv in 23 pv in 24 pv in 25 sw 26 27 sgnd 28 29 run/ss 30 sgnd 31 sgnd 32 pgnd 64 pgnd 63 pgnd 62 pgnd 61 pgnd 60 pgnd 59 pgnd 58 pgnd 57 pgnd 56 sw 55 intv cc intv cc 54 intv cc intv cc 53 sv in v in 52 sv in 51 sgnd 50 sgnd 49 pgnd 1 pgnd 2 pgnd 3 sw 4 sw 5 sw 6 sw 7 sw 8 sw 9 sw 10 sw 11 pv in v in 12 pv in 13 pv in 14 pv in 15 pv in 16 3610 ta05 c f 0.1f 25v r f1 1 c vcc 4.7f 6.3v c on 0.01f c4 0.01f c2 c1 run/ss c ss 0.1f v in r ss1 510k (optional) (optional) (optional) r1 1.58k 1% r2 30.1k 1% r pg1 100k r on 1m 1% r5 20k c c1 560pf c c2 100pf (optional) c von (optional) (optional) r von nc d b cmdsh-3 sw boost intv cc c b1 0.22f r elate d p arts t ypical a pplication 14v to 24v input to 12v/5a at 500khz part number description comments ltc1778 no r sense current mode synchronous step-down controller up to 97% effciency, v in : 4v to 36v, 0.8v v out (0.9)(v in ), i out up to 20a ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out = 0.8v, i q = 60a, i sd <1a, ms package ltc3412 2.5a (i out ) 4mhz synchronous step-down dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60ma, i sd <1ma, tssop16e ltc3414 4a (i out ), 4mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd <1a, tssop20e package ltc3418 8a (i out ), 4mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, thermally enhanced 38-lead qfn package ltc3770 fast, no r sense step-down synchronous controller with margining, tracking, pll 0.67% 0.6v reference voltage; programmable margining; true current mode; 4v v in 32v ltc3778 low v out , no r sense synchronous step-down controller 0.6v v out (0.9) v in , 4v v in 36v, i out up to 20a lt3800 60v synchronous step-down controller current mode, output slew rate control ltm4600hv 10a complete switch mode power supply 92% effciency, v in : 4.5v to 28v, v out = 0.6v, true current mode control, ultrafast transient response ltm4601hv 12a complete switch mode power supply 92% effciency, v in : 4.5v to 28v, v out = 0.6v, true current mode control, ultrafast transient response ltm4602hv 6a complete switch mode power supply 92% effciency, v in : 4.5v to 28v, v out = 0.6v, true current mode control, ultrafast transient response ltm4603hv 6a complete switch mode power supply 93% effciency, v in : 4.5v to 28v, with pll, output tracking and margining

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